High-Speed Binary-to-Residue Converter Design Using 2-Bit Segmentation of the Input Word

Authors

DOI:

https://doi.org/10.26408/124.04

Keywords:

Binary-to-residue conversion, residue number system, FPGA

Abstract

In this paper a new approach to the design of the high-speed binary-to-residue converter is proposed that allows the attaining of high pipelining rates by eliminating memories used in modulo m generators. The converter algorithm uses segmentation of the input binary word into 2-bit segments. The use and effects of the input word segmentation for the synthesis of converters for five-bit moduli are presented. For the number represented by each segment, the modulo m reduction using a segment modulo m generator is performed. The use of 2-bit segments substantially reduces the hardware amount of the layer of input modulo m generators. The generated residues are added using the multi-operand modulo m adder based on the carry-save adder (CSA) tree, reduction of the number represented by the output CSA tree vectors to the 2m range and fast two-operand modulo m additions. Hardware amount and time delay analyses are also included.

References

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Published

2022-12-31

How to Cite

Smyk, R., & Czyżak, M. (2022). High-Speed Binary-to-Residue Converter Design Using 2-Bit Segmentation of the Input Word. Scientific Journal of Gdynia Maritime University, (124), 42–56. https://doi.org/10.26408/124.04

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